A 36 Years Perspective of HPC’s 100 Billion Performance Improvement and Some Thoughts on What Comes Next
Mark Seager, Intel Fellow, Fellow in Residence for Intel China, Director of HPC Strategy, CTO for the Technical Computing Ecosystem.
Intel, Inc. San Francisco, California, USA
We will provide a historical perspective on the advances in HPC hardware and software over the last 36 years: 1’s MegaFLOP/s to 100’s of PetaFLOP/s and proprietary or homegrown software stacks to open source almost everything. We will also discuss applications that were enabled as a result in this 100 billion fold increase in computational capability. We will also discuss how this has fundamentally changed scientific discovery twice and enabled a vast number of industry advances, society changes, improvement of human condition.
Looking forward we will discuss the HPC+AI+HPDA converged workflows and how this is informing both computational scientific discovery and the broader coupling with and informing experimental and theoretical aspects of the scientific method. The converged workflows are also being driven by the virtuous cycle dynamic between converged workflow advances and the digital economy transformation. This converged workflow and the arrival of diverse computing architectures is profoundly challenging both system architecture and applications development practices. Many industry participants are indicating that the rate of Moore’s law improvement is slowing down and will come to an inevitable near term end. We will discuss several reasons why this alarm is not well founded, and is eerily similar to the inaccurate near term “peak oil” production predictions over the last 20+ years.
Thursday 14th February 2019, 3:30 pm – 4:15 pm – Schedule
Intel Fellow, Director of HPC Strategy
Mark leads Scale out strategy for Intel’s Exascale Computing Organization. Mark is also a Fellow in Residence for Intel China. At Intel he is working on an ecosystem approach to develop and build HPC and cloud systems with Exascale capabilities. Mark was instrumental in the development of Intel’s Scalable System Framework.
Before moving to Intel, he was assistant department head for Advanced Computing Technology within the Integrated Computing and Communications department at Lawrence Livermore National Laboratory (LLNL). He joined LLNL in 1983 and has been working in parallel processing ever since.
He has won numerous awards including the prestigious Edward Teller Award for “major contributions to the state-of-the-art in high performance computing.” In 2015 he was promoted to Intel Fellow. Mark and Jan Seager breed and raise Arabian horses, with one national championship win in 2013.
He received a BS degree in mathematics and astrophysics from the University of New Mexico at Albuquerque and a PhD in numerical analysis from the University of Texas at Austin.