Samantika Sury is a Principal Engineer in Intel. She has led several HPC projects for USG customers and is currently the Principal Investigator for a U.S. Department of Energy project called Path Forward.
Her expertise in parallel architectures produced some of the first architectural insights demonstrating that uncore bottlenecks impacted thread scalability and parallel program performance. She has led architecture on several technologies that improve the scalability of Intel servers.
She is an inventor on more than 20 patents and an author on several papers in memory hierarchies, cache coherence & machine learning.
“Addressing Challenges in Data movement and Communication”
Principal Engineer, Intel Corp.
Westford, Massachusets, USA
Thursday 20 February 2020 – 10:55 am
While the last decade of computer architecture has established many novel compute solutions we find that application performance is often dominated by data movement. The convergence of HPC, AI and analytics and emergence of edge computing has furthered the trend of applications needing to access large amounts of memory fast and efficiently and with low energy.
In this talk we demonstrate the performance and power impact of data movement on key parallel applications and explore architectural solutions like tightly coupled heterogeneity, moving compute to data and adaptive hardware to address the performance challenges due to data movement.