Chief Computer Scientist, PNNL. US.
“The Democratization of Co-design“
20 February 2025
Abstract
The U.S. CHIPS R&D programs are creating an infrastructure for microelectronics prototyping and advanced packaging. This CHIPS infrastructure provides an unprecedented opportunity to create a low cost, agile, prototype hardware design and generation capability. This talk will provide an overview of a new DOE project that integrates capabilities to democratize the hardware-software co-design process—DeCoDe. We build on our history of compiler framework optimization to map domain specialized applications to high level synthesis tools; and integrate capabilities from many collaborators to both leverage from, and create our contribution back to, an open hardware technology commons.
Some highlights from this overview include, target converged application co-design drivers, leverage the open chiplet ecosystem to demonstrate heterogeneous computing where customized prototype designs are concentrated in only a few chiplets, support hardware composition with corresponding system software, and use prototype heterogeneous processor hardware to quantify improvements in energy efficiency. Our focus on low cost and agile hardware R&D defines boundaries on what DeCoDe can and cannot do. We work with open source hardware design tools to minimize the cost of commercial EDA tools and to benefit from open data sets, we leverage the open chiplet ecosystem to integrate our custom hardware designs with a much larger number of existing computing chiplets, and finally, we stay focused on hardware design for prototypes to support lab-to-fab R&D and validate ideas that industry might later bring to product.
Bio
Antonino Tumeo received the M.S. degree in Informatic Engineering, in 2005, and the Ph.D degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. He is a Chief Scientist in the Future Computing Technologies Group at Pacific Northwest National Laboratory (PNNL), which he joined in 2009 as a post-doctoral research associate. Previously, he was a post-doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high-performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing. Dr. Tumeo is currently leading several projects focused on the synthesis of custom accelerators for various workloads starting from high-level programming frameworks as well as on the design of compiler frameworks for novel computing paradigms. He is a Senior Member of the IEEE and of the ACM.
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