James Ang

Chief Scientist for Computing in the Physical & Computational Sciences Directorate, Pacific Northwest National Laboratory (PNNL). US.

“Crossing the Valley of Death via a CHIPS-enabled Renaissance in Co-design“

Abstract

One of the greatest challenges in microelectronics computing R&D is the difference in the time and cost associated with the development of hardware capabilities versus the development of software capabilities. The shorter timelines and significantly lower costs associated with software development have traditionally made it much more attractive for venture capital (VC) investment. Addressing this challenge is a goal of the U.S. CHIPS and Science Act of 2022––to help fundamental semiconductor and microelectronics R&D Cross the Valley of Death and bridge the gap to innovative products. The Department of Commerce CHIPS Act is making two key R&D investments. Firstly, establishing the National Center for Advancement of Semiconductor Technology (NatCAST)¹ to deploy an infrastructure to support the rapid and low cost design and development of prototype hardware. Secondly, employing the National Advanced Packaging Manufacturing Program (NAPMP) to support R&D in advanced packaging and 3D heterogeneous integration. These infrastructure capabilities can then lower the technical risk that VCs or U.S. federal programs face when evaluating innovative computing solutions.

In this talk, I will share a vision of greatly lowered barriers to innovation––where 100x reductions in time and cost to develop prototype computing hardware designs are feasible. Between lab concepts and actual products , intermediate proof-of-concept test hardware can be produced by NatCAST’s prototyping infrastructure. While these test hardware designs could be developed with traditional “product grade” hardware design tools, a practical approach would be to use more agile, “prototype grade” design tools that have sufficient fidelity to create small amounts of computing hardware chiplets for R&D. The NAPMP support for standardization of chiplet interfaces will enable a prototype hardware test-and-evaluation strategy that leverages a portfolio of interoperable chiplet designs to further reduce costs of computing R&D. Validated chiplets from this portfolio can be packaged with new NatCAST-fabricated, domain-specialized prototype accelerator chiplets to create a heterogeneous processor for evaluation with co-designed supporting software. Quantitatively evaluating the performance, energy efficiency and cybersecurity robustness of these prototype heterogeneous processors will lower the technical risks associated with selecting the best designs for bridging to product grade hardware designs.

¹ https://natcast.org/

Bio

Jim is the Chief Scientist for Computing in the Physical and Computational Sciences Directorate (PCSD) at Pacific Northwest National Laboratory (PNNL), where he serves as the lab lead for the U.S. DOE, Office of Science (DOE/SC), Advanced Scientific Computing Research (ASCR) Program. PNNL’s ASCR portfolio includes over 20 R&D projects in applied mathematics, computer science, advanced architectures, 5G networking, and computational modeling and simulation. Jim’s computing leadership role also intersects with upstream technology challenges associated with microelectronics and semiconductors.

Shortly after joining PNNL, Jim helped organize the October 2018 DOE/SC workshop on Basic Research Needs for Microelectronics. The goal was to identify DOE’s Microelectronics R&D priorities for the next decade and beyond. This experience led to an invitation to serve on the executive committee for the Semiconductor Research Corporation (SRC) Decadal Plan. Several SRC workshops were held on topics that included, energy-efficient computing, networking and communications, analog electronics, memory and storage, and hardware support for cybersecurity and privacy. The outcomes of these workshops were documented in the SRC Decadal Plan report that describes the seismic shifts that will drive industry R&D challenges. Jim was recently appointed by the U.S. Commerce Secretary to serve on the DOC/NIST Industrial Advisory Committee to provide input on R&D gaps to address by the CHIPS and Science Act.

Click to download 2024 Slides in pdf.